RISC-V /Debug /Trigger Data 1 (64-bit tdata1)

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Interpret as Trigger Data 1 (64-bit tdata1)

63 6059 5655 5251 4847 4443 4039 3635 3231 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0data0 (both)dmode 0 (none)type

type=none, dmode=both

Description

This register provides access to the trigger selected by {csr-tselect}. The reset values listed here apply to every underlying trigger.

This register is optional if no triggers are implemented.

Writing 0 to this register must result in a trigger that is disabled. If this trigger supports multiple types, then the hardware should disable it by changing {tdata1-type} to 15.

Fields

data

If {tdata1-type} is 0, then this field is hard-wired to 0.

Trigger-specific data.

dmode

If {tdata1-type} is 0, then this bit is hard-wired to 0.

0 (both): Both Debug and M-mode can write the tdata registers at the selected {csr-tselect}.

1 (dmode): Only Debug Mode can write the tdata registers at the selected {csr-tselect}. Writes from other modes are ignored.

type

0 (none): There is no trigger at this {csr-tselect}.

1 (legacy): The trigger is a legacy SiFive address match trigger. These should not be implemented and aren’t further documented here.

2 (mcontrol): The trigger is an address/data match trigger. The remaining bits in this register act as described in {csr-mcontrol}.

3 (icount): The trigger is an instruction count trigger. The remaining bits in this register act as described in {csr-icount}.

4 (itrigger): The trigger is an interrupt trigger. The remaining bits in this register act as described in {csr-itrigger}.

5 (etrigger): The trigger is an exception trigger. The remaining bits in this register act as described in {csr-etrigger}.

6 (mcontrol6): The trigger is an address/data match trigger. The remaining bits in this register act as described in {csr-mcontrol6}. This is similar to a type 2 trigger, but provides additional functionality and should be used instead of type 2 in newer implementations.

7 (tmexttrigger): The trigger is a trigger source external to the TM. The remaining bits in this register act as described in {csr-tmexttrigger}.

14 (custom): These trigger types are available for non-standard use.

14 (custom): These trigger types are available for non-standard use.

14 (custom): These trigger types are available for non-standard use.

15 (disabled): This trigger is disabled. In this state, {csr-tdata2} and {csr-tdata3} can be written with any value that is supported for any of the types this trigger implements. The remaining bits in this register, except for {tdata1-dmode}, are ignored.

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